beq

Branch to PC + imm if the value in register xs1 is equal to the value in register xs2. Raise a `MisalignedAddress` exception if PC + imm is misaligned.

Synopsis

beq xs1, xs2, imm

Pseudo-Instruction beqz xs1, imm
            equals beq xs1, 0, imm
              when xs2 == 0

Encoding

Type:

funct3: 000

opcode: 1100011

RISC-V Instruction Encoder/Decoder

open beq in rvcodecjs

Availability

Extension: I
Base: RV32 + RV64