blt

Branch to PC + imm if the signed value in register xs1 is less than the signed value in register xs2. Raise a `MisalignedAddress` exception if PC + imm is misaligned.

Synopsis

blt xs1, xs2, imm

Pseudo-Instruction bltz xs1, imm
            equals blt xs1, 0, imm
              when xs2 == 0

Pseudo-Instruction bgtz xs2, imm
            equals blt 0, xs2, imm
              when xs1 == 0

Pseudo-Instruction bgt xs2, xs1, imm
            equals blt xs1, xs2, imm
              when true

Encoding

Type:

funct3: 100

opcode: 1100011

RISC-V Instruction Encoder/Decoder

open blt in rvcodecjs

Availability

Extension: I
Base: RV32 + RV64