bltu

Branch to PC + imm if the unsigned value in register xs1 is less than the unsigned value in register xs2. Raise a `MisalignedAddress` exception if PC + imm is misaligned.

Synopsis

bltu xs1, xs2, imm

Pseudo-Instruction bgtu xs2, xs1, imm
            equals bltu xs1, xs2, imm
              when true

Encoding

Type:

funct3: 110

opcode: 1100011

RISC-V Instruction Encoder/Decoder

open bltu in rvcodecjs

Availability

Extension: I
Base: RV32 + RV64