Load 32 bits of data from the address in `xs1` into register `xd`, sign-extending the result to XLEN bits. This instruction has both acquire and release semantics. No subsequent memory operations (in program order) from this hart can be observed to occur before this load completes, and no previous memory operations can be observed to occur after this load completes. The address must be naturally aligned (4-byte aligned); if not, an address-misaligned or access-fault exception will be raised.
lw.aqrl xd, (xs1)Type: