Store the lowest 8 bits of register `xs2` to the address in `xs1`. This instruction has both acquire and release semantics. No subsequent memory operations (in program order) from this hart can be observed to occur before this store completes, and no previous memory operations can be observed to occur after this store completes. The address must be naturally aligned; if not, an address-misaligned or access-fault exception will be raised.
sb.aqrl xs2, (xs1)Type: