csrrs

Atomically read and set bits in a CSR. Reads the value of the CSR, zero-extends the value to `XLEN` bits, and writes it to integer register `xd`. The initial value in integer register `xs1` is treated as a bit mask that specifies bit positions to be set in the CSR. Any bit that is high in `xs1` will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. Other bits in the CSR are not explicitly written.

Synopsis

csrrs xd, csr, xs1

Pseudo-Instruction frflags xd
            equals csrrs xd, 0x001, 0
              when xs1 == 0 && csr == 0x001

Pseudo-Instruction frrm xd
            equals csrrs xd, 0x002, 0
              when xs1 == 0 && csr == 0x002

Pseudo-Instruction frcsr xd
            equals csrrs xd, 0x003, 0
              when xs1 == 0 && csr == 0x003

Pseudo-Instruction rdcycle xd
            equals csrrs xd, 0xC00, 0
              when xs1 == 0 && csr == 0xC00

Pseudo-Instruction rdtime xd
            equals csrrs xd, 0xC01, 0
              when xs1 == 0 && csr == 0xC01

Pseudo-Instruction rdinstret xd
            equals csrrs xd, 0xC02, 0
              when xs1 == 0 && csr == 0xC02

Pseudo-Instruction rdcycleh xd
            equals csrrs xd, 0xC80, 0
              when xs1 == 0 && csr == 0xC80

Pseudo-Instruction rdtimeh xd
            equals csrrs xd, 0xC81, 0
              when xs1 == 0 && csr == 0xC81

Pseudo-Instruction rdinstreth xd
            equals csrrs xd, 0xC82, 0
              when xs1 == 0 && csr == 0xC82

Pseudo-Instruction csrr xd, csr
            equals csrrs xd, csr, 0
              when xs1 == 0

Pseudo-Instruction csrs csr, xs1
            equals csrrs 0, csr, xs1
              when xd == 0

csrrs

Synopsis

Encoding

RISC-V Instruction Encoder/Decoder

Availability