aes64esm

Uses the two 64-bit source registers to represent the entire AES state, and produces _half_ of the next round output, applying the Inverse ShiftRows, SubBytes and MixColumns steps.

Synopsis

aes64esm xd, xs1, xs2

Encoding

Type: R

0671112141519202425310110011xd000xs1xs20011011
funct7: 0011011
funct3: 000
opcode: 0110011

RISC-V Instruction Encoder/Decoder

open aes64esm in rvcodecjs

Availability