For RV64, AMOCAS.Q atomically loads 128-bits of a data value from address in xs1, compares the loaded value to a 128-bit value held in a register pair consisting of xd and xd+1, and if the comparison is bitwise equal, then stores the 128-bit value held in the register pair xs2 and xs2+1 to the original address in xs1. The value loaded from memory is placed into the register pair xd and xd+1. The instruction requires the first register in the pair to be even numbered; encodings with odd-numbered registers specified in xs2 and xd are reserved. When the first register of a source register pair is x0, then both halves of the pair read as zero. When the first register of a destination register pair is x0, then the entire register result is discarded and neither destination register is written. Just as for AMOs in the A extension, AMOCAS.Q requires that the address held in xs1 be naturally aligned to the size of the operand (i.e., sixteen-byte aligned for quadwords). And the same exception options apply if the address is not naturally aligned. Just as for AMOs in the A extension, the AMOCAS.Q optionally provides release consistency semantics, using the aq and rl bits, to help implement multiprocessor synchronization. The memory operation performed by an AMOCAS.Q, when successful, has acquire semantics if aq bit is 1 and has release semantics if rl bit is 1. The memory operation performed by an AMOCAS.W/D/Q, when not successful, has acquire semantics if aq bit is 1 but does not have release semantics, regardless of rl. A FENCE instruction may be used to order the memory read access and, if produced, the memory write access by an AMOCAS.Q instruction. [Note] An unsuccessful AMOCAS.Q may either not perform a memory write or may write back the old value loaded from memory. The memory write, if produced, does not have release semantics, regardless of rl. An AMOCAS.Q instruction always requires write permissions.
amocas.q xd, xs2, (xs1)Type: R