beq

Branch to PC + imm if the value in register xs1 is equal to the value in register xs2. Raise a `MisalignedAddress` exception if PC + imm is misaligned.

Synopsis

beq xs1, xs2, imm

Encoding

Type:

0678111214151920242530311100011immimm000xs1xs2immimm
funct3: 000
opcode: 1100011

RISC-V Instruction Encoder/Decoder

open beq in rvcodecjs

Availability