blt

Branch to PC + imm if the signed value in register xs1 is less than the signed value in register xs2. Raise a `MisalignedAddress` exception if PC + imm is misaligned.

Synopsis

blt xs1, xs2, imm

Encoding

Type:

0678111214151920242530311100011immimm100xs1xs2immimm
funct3: 100
opcode: 1100011

RISC-V Instruction Encoder/Decoder

open blt in rvcodecjs

Availability