divw

Divide the lower 32-bits of register xs1 by the lower 32-bits of register xs2, and store the sign-extended result in xd. The remainder is discarded. Division by zero will put -1 into xd. Division resulting in signed overflow (when most negative number is divided by -1) will put the most negative number into xd;

Synopsis

divw xd, xs1, xs2

Encoding

Type: R

0671112141519202425310111011xd100xs1xs20000001
funct7: 0000001
funct3: 100
opcode: 0111011

RISC-V Instruction Encoder/Decoder

open divw in rvcodecjs

Availability