fence

Orders memory operations. The `fence` instruction is used to order device I/O and memory accesses as viewed by other RISC-V harts and external devices or coprocessors. Any combination of device input (I), device output (O), memory reads \(R), and memory writes (W) may be ordered with respect to any combination of the same. Informally, no other RISC-V hart or external device can observe any operation in the _successor_ set following a `fence` before any operation in the _predecessor_ set preceding the `fence`. The predecessor and successor fields have the same format to specify operation types: [%autowidth] |=== 4+| `pred` 4+| `succ` | 27 | 26 |25 | 24 | 23 | 22 | 21| 20 | PI | PO |PR | PW | SI | SO |SR | SW |=== [%autowidth,align="center",cols="^1,^1,<3",options="header"] .Fence mode encoding |=== |_fm_ field |Mnemonic |Meaning |0000 |_none_ |Normal Fence |1000 |TSO |With `FENCE RW,RW`: exclude write-to-read ordering; otherwise: _Reserved for future use._ 2+|_other_ |_Reserved for future use._ |=== When the mode field _fm_ is `0001` and both the predecessor and successor sets are 'RW', then the instruction acts as a special-case `fence.tso`. `fence.tso` orders all load operations in its predecessor set before all memory operations in its successor set, and all store operations in its predecessor set before all store operations in its successor set. This leaves non-AMO store operations in the 'fence.tso's predecessor set unordered with non-AMO loads in its successor set. When mode field _fm_ is not `0001`, or when mode field _fm_ is `0001` but the _pred_ and _succ_ fields are not both 'RW' (0x3), then the fence acts as a baseline fence (_e.g._, _fm_ is effectively `0000`). This is unaffected by the FIOM bits, described below (implicit promotion does not change how `fence.tso` is decoded). The `xs1` and `xd` fields are unused and ignored. In modes other than M-mode, `fence` is further affected by `menvcfg.FIOM`, `senvcfg.FIOM`<% if ext?(:H) %>, and/or `henvcfg.FIOM`<% end %> as follows: .Effective PR/PW/SR/SW in (H)S-mode [%autowidth,cols=",,,",options="header",separator="!"] !=== ! [.rotate]#`menvcfg.FIOM`# ! `pred.PI` + `pred.PO` + `succ.SI` + `succ.SO` ! -> + -> + -> + -> ! effective `PR` + effective `PW` + effective `SR` + effective `SW` ! 0 ! - ! ! from encoding ! 1 ! 0 ! ! from encoding ! 1 ! 1 ! ! 1 !=== .Effective PR/PW/SR/SW in U-mode [%autowidth,options="header",separator="!",cols=",,,,"] !=== ! [.rotate]#`menvcfg.FIOM`# ! [.rotate]#`senvcfg.FIOM`# ! `pred.PI` + `pred.PO` + `succ.SI` + `succ.SO` ! -> + -> + -> + -> ! effective `PR` + effective `PW` + effective `SR` + effective `SW` ! 0 ! 0 ! - ! ! from encoding ! 0 ! 1 ! 0 ! ! from encoding ! 0 ! 1 ! 1 ! ! 1 ! 1 ! - ! 0 ! ! from encoding ! 1 ! - ! 1 ! ! 1 !=== <%- if ext?(:H) -%> .Effective PR/PW/SR/SW in VS-mode and VU-mode [%autowidth,options="header",separator="!",cols=",,,,"] !=== ! [.rotate]#`menvcfg.FIOM`# ! [.rotate]#`henvcfg.FIOM`# ! `pred.PI` + `pred.PO` + `succ.SI` + `succ.SO` ! -> + -> + -> + -> ! effective `PR` + effective `PW` + effective `SR` + effective `SW` ! 0 ! 0 ! - ! ! from encoding ! 0 ! 1 ! 0 ! ! from encoding ! 0 ! 1 ! 1 ! ! 1 ! 1 ! - ! 0 ! ! from encoding ! 1 ! - ! 1 ! ! 1 !=== <%- end -%>

fence pred, succ